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Sahu, Anil Kumar
- A Code Width Built In Self-Test Circuit for Eight Bit Sigma Delta ADC
Authors
1 Department of ETC, SSTC, SSGI (FET), Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 8, No 4 (2016), Pagination: 93-96Abstract
The paper presented here exhibits a modern ADC (analog-to-digital converter) BIST (built-in self test) scheme using code-width with sample difference testing technique. The BIST scheme proposed here is employed on 8-bit sigma-delta ADC which is implemented by using first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter. The proposed BIST scheme is certified by simulation of the 8 bit sigma-delta ADC with arbitrary faults. The measurements of Differential Non Linearity (DNL), monotonicity fault and missing code fault have been detected. Power consumed in the proposed BIST circuit is 18mW for the given power supply of 1V. The output is shown at the output of OR gate denoted as 'F'. In order to implement the BIST scheme considered in this paper, an 8 sigma-delta ADC and also the other components were designed in Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology.
Keywords
BIST, BSIM4, Code Width, DNL, Missing Code Fault, Monotonicity Fault.
- A Fourth Order 1.8V Power Supply Loop Filter in Continuous Time Delta-Sigma ADC Implemented in 0.18-um CMOS Technology
Authors
1 SSGI, Bhilai, IN
Source
Digital Signal Processing, Vol 8, No 4 (2016), Pagination: 98-102Abstract
The use of a fourth order loop filter within a Continuous-Time (CT) ΔΣ Analog-to-Digital Converter (ADC) structure is explored and a custom prototype in a 0.18μm CMOS with a measured performance of 40dB gain, 70 degree phase margin and unity gain bandwidth of 79.060 MHz which consuming low power consumption at 1.8V power supply. A key innovation is the explicit use of the loop filter output to avoid the signal distortion that had severely limited the performance of ΔΣ ADC's. The proposed architecture consists of the loop filter using active RC integrators in a low power. This study is implemented in Tanner Tools by using 0.18μm CMOS process.Keywords
Analog to Digital Converter (ADC), Operational Amplifier (OPAMP), Resistor Capacitor (RC) Integrator.- A 6.7mW 8-Bit Power Optimzed Sigma-Delta ADC as DUT for Built-in-Self-Test in 45nm CMOS
Authors
1 Department of ETC, Shri Shankaracharaya Technical Campus (SSTC), Bhilai, IN
2 Department of EEE, Chhatrapati Shivaji Institute of Technology, Durg, IN
Source
Programmable Device Circuits and Systems, Vol 8, No 3 (2016), Pagination: 61-66Abstract
Design and testing of oversampling sigma-delta (ΣΔ) Analog to digitals converter is graeat challenge is in todays mixed signal ICs . In this paper a contemporary design for 8-bit ΣΔoversampling ADC is presented, in which first order oversampling ΣΔ modulator and the decimation filter is second order CIC (Cascaded Integrated Comb) filter which is used. Transistor level circuit design and output simulation of the sigma-delta ADC with a power supply of 1V is presented here. This architecture is implemented by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology is used as DUT (design under test )block of Built -in -self -test realization of ADC.
Keywords
8-Bit Sigma-Delta ADC, CIC, Sigma Delta Modulator.- Design of 64x64 Bit Parity Preserving Reversible Vedic Multiplier Using Carry Look Ahead Adder
Authors
1 SSTC, Bhilai, IN
Source
Networking and Communication Engineering, Vol 7, No 6 (2015), Pagination: 247-254Abstract
Multiplier play an important role in most of signal processing operations, processors and nanotechnology, quantum computing .The performance of the multiplier is depend upon architecture and the algorithm used for the multiplication operations .The Carry Look ahead Adder is implemented using fault tolerant gate, employed for the partial product addition which is constructed using New fault tolerant Gate (NFT) and Double Feynman gate (F2G). A 64x64 bit fault tolerant and high speed multiplier architecture is proposed. The newly proposed multiplier architecture is based on Urdhva Tiryakbhayam formula from an ancient Indian Vedic Mathematics which produce all partial product and theirs addition in one step and Parity Preserving reversible gate which performs a reversible computation which ensures zero internal power dissipation in a manner that they also detect a fault in the circuit. A newly proposed multiplier have its application in the field of quantum computing, processors, nanotechnology, and Digital Signal Processing. The design of high speed parity preserving reversible vedic multiplier architecture is done in Verilog language and simulated using Xilinx14.7.Keywords
Carry Look Ahead Adder, Fault Tolerant Property, Delay, Urdhav Tiryakbhayam Method.- Hardware Efficient Transceiver Microcell Architecture of USB 2.0 for High Speed Data Communication Using FPGA
Authors
1 SSTC, Bhilai, IN
Source
Digital Signal Processing, Vol 7, No 4 (2015), Pagination: 102-105Abstract
In this paper USB 2.0 transceiver architecture using innovative approach presented for high speed data communication. Implemented Universal Serial Bus (USB) Transceiver Macro cell is well suited for high speed data communication and also capable of handling data output relative to input as high as what USB 2.0 demands. Design is implemented on hardware of a Spartan-3FPGA. High-speed to access peripheral interfaces like USB 2.0 is coded in Veriog HDL. Result shown paper hardware efficient and test bench verification is done.Keywords
USB.2.0, Transmitter, Receiver.- Design and Development of Output Response Analyzer for the BIST of Sigma-Delta Modulator
Authors
1 SSTC, Bhilai, IN
Source
Digital Signal Processing, Vol 7, No 4 (2015), Pagination: 106-111Abstract
Testing of high resolution second order sigma delta (ΣΔ) modulator is a very expensive process. With the advanced technology, where the complexity over a small area is increasing, then testing at low cost with good accuracy is becoming a tedious issue for the manufacturing process. The cost effectiveness can be calculated on the basis of different parameters of the ΣΔ modulator such as SNDR, ENOB, Gain, Offset, THD, SNR etc. Testing time also play an important role in the cost effectiveness of the modulator. The Built-in-self-test (BIST) allows the machine or circuit to test itself. BIST is desirable for the VLSI system in order to reduce the cost per chip of production-time testing by the manufacture, it can also provide the means to perform in-the field diagnostic. Therefore, this paper will demonstrate a possibility to simplify modeling and simulation of testing strategy of high-resolution ΣΔ modulator using MATLAB SIMULINK environment. Here, we are finding the cost effectiveness on the basis of Signal to Noise Distortion Ratio (SNDR) for the ΣΔ modulator BIST. A ΣΔ modulation based signal generator is considered which can produce analog sinusoidal test stimuli and digital reference signal on chip. By comparing the ADC output with that of the generator reference signal, the parameter can be determined on chip based on the standard equations in the proposed simulation environment.Keywords
Sigma-Delta Modulator (ΣΔ), Signal-To-Noise Ratio (SNR), Output Response Analyzer (ORA), Integrated Nonlinearity Error (INL), Built-In-Self Test (BIST), Dynamic Nonlinearity Error (DNL).- Comparative Analysis of Pipelined SHA-1 Algorithm based on Different Methodologies
Authors
1 Department of ETC, SSTC, SSGI (FET), Bhilai, IN
Source
Biometrics and Bioinformatics, Vol 8, No 4 (2016), Pagination: 83-88Abstract
This paper exhibits pipelined Secure Hash Algorithm (SHA-1) architecture based on different methodologies. Three pipelined architecture based on Iterative, Loop unfolding and Pre-Computation technique are implemented. It also focuses on the minimization on critical path delay by employing fastest adder. The performance of proposed architectures are compared and analyzed in terms of number of slices, operating frequency and throughput. The design and implementation work is performed using VHDL in Xilinx ISE Design Suite 13.2 tool. The proposed implementations are also compared with some previous works and offer better results.
Keywords
Iterative, Loop Unfolding, Pre-Computation, Pipelining, Secure Hash Algorithm (SHA-1).- Low Noise Elliptical Filter in 250 Nanometer Technology for EEG Signals
Authors
Source
Digital Signal Processing, Vol 8, No 5 (2016), Pagination: 126-129Abstract
A low noise filter for low frequency is presented. 5th order elliptical Filter design using OTA-C method is low in noise and good to acquire biopotential signal in range of 40 Hz. Filter provides strong attenuation against power line interference which occurs due to power supply of a system. For achieving low noise and low transconductance, current division and current cancellation technique (CDCC) is applied.
Filters also have a total harmonic distortion of 1.6 % with 50 millivolt peak to peak signals. OTA used CDCC topology provide the low transconductance required for low frequency application. OTA work in sub threshold region with bias current of 300 Nano amperes and also have a tuning ability with vtune voltage and it is biased with simple current mirror. This entire circuit design in 250 nanometer technology with 2.5 volt power supply using T-SPICE simulator of tanner EDA 15. Bandwidth and noise of a filter is 38 Hz, 3.36µvolt/ respectively.
Keywords
Current Division Current Cancellation (CDCC), Electronic Design Automation (EDA), Operational Transconductance Amplifier (OTA), Special Programed for Integrated Circuit Emphasis (SPICE).- Design of Low Power VCO Enabled Quantizer in Continuous Time Sigma Delta ADC for Signal Processing Application
Authors
1 Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Group of Institutions (FET), IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 1 (2016), Pagination: 193-197Abstract
An accurate design of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time Sigma Delta ADC in 180nm CMOS technology using Tanner EDA tools is done. The proposed architecture consists of the loop filter, VCO quantizer and the DAC in the feedback side of model. The Operational Amplifier (OPAMP) used in design of loop filters offers 40dB gain, 70 degree phase margin and unity gain bandwidth of 79.06MHz. Even order harmonics of VCO are reduced by VCO quantizer loop structures. The Higher order loop filter is designed using an active Resistance and Capacitive based integrators and VCO quantizer is implemented using 15 multiple stage ring oscillator and register of DFF which provides an added advantage of low phase noise with frequency of 100 KHz rang. Remarkable power dissipation of overall circuit is 3.8 mW.Keywords
Analog to Digital Converter (ADC), Operational Amplifier (OPAMP), Nonidealities, Voltage Controlled Oscillator (VCO).- New Frontier and the Advanced Herbal Approaches for the Treatment of Lymphatic Filariasis
Authors
1 University Institute of Pharmacy, Pt. Ravishankar Shukla University, Raipur (C.G.), IN
Source
Research Journal of Pharmacology and Pharmacodynamics, Vol 7, No 4 (2015), Pagination: 196-198Abstract
Lymphatic filariasis causes serious health problems in tropical and subtropical developing countries of the world and more than 1.3 billion people are infected. Lymphatic filariasis is disease targeted for elimination by global programme. Global elimination programme have two main objectives one is drug transmission of the parasites and another to provide care for those with the disease. Mass drug administration plays a major for the transmission interruption of disease. Modern synthetic drugs found to be very effective for that purpose, but cause lots of side effects. A large no. of medicinal plants have been claimed to have good antifilarial activity and less side effects. The present review summarizes some present treatment strategies and preliminary studies on herbal approaches of filariasis treatment, which can be investigated further to search of novel herbal drugs to treat filariasis.Keywords
Filariasis, Lymphatic Filariasis, Herbal Drug, Filariasis Treatment.- Modeling of Test Stimulus Generator and CORDIC Logic for Testing of CT Sigma Delta Analog-To-Digital Converter
Authors
1 Department of ETC, Shri Shankaracharaya Technical Campus (SSTC), Bhilai, IN
2 Department of EEE, Chhatrapati Shivaji Institute of Technology, Durg, IN
3 International Institute of Information Technology (IIIT), Bangalore, IN
Source
Fuzzy Systems, Vol 10, No 4 (2018), Pagination: 99-102Abstract
This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK tool environment. Stimuli are applied into the design under test and extract the important static and transmission parameters by means of the response analyzer. There are so many types of stimulus which have different types of properties. Therefore, the test stimuli generator is a key building block in BIST methodology and must be high quality, flexible and easy to realize.Output Response Analyzer (ORA) is most important component in Built-In-Self-Test (BIST) architecture of CT sigma delta ADC. There are many techniques of ORA used for determining performance matrix parameter such as integral non-linearity, differential non-linearity and Signal-to-Noise Ratio (SNR).In this paper suggests CORDIC technique as ORA and it’s modelling and simulation has been implemented on MATLAB simulink tool environment. The COrdinate Rotation Digital Computer (CORDIC) logic is used to reduces the design complexity of circuit.
Keywords
CT Sigma-Delta ADC Structrure, Test Stimuli Generator, Cordinate Rotation Digital Computer (CORDIC) Logic for ORA, Built-In-Self-Test for CT ADC.References
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- Power-Efficient Montgomery Modular Multiplication Review Using VLSI Architecture
Authors
Source
Programmable Device Circuits and Systems, Vol 10, No 6 (2018), Pagination: 108-112Abstract
In Public key Cryptosystem like RSA and Elliptic Curve Cryptography (ECC), modular multiplication is a basic operation. A famous method to execute modular multiplication in hardware circuit is based on the Montgomery modular multiplication it has several benefits. Many Montgomery Modular multiplication hardware architecture and algorithm employ carry-save addition (CSA), to speed up the encryption/decryption process. An adiabatic logic brings about great deal of power minimization in digital circuit. This research paper presents a review of previous work done on modular multiplication and suggest a new CSA based Montgomery modular multiplier architecture designed utilizing adiabatic logic to make it low power consuming as compare to CMOS-Logic circuit.